Verilog code for adders/subtractors

Following is the Verilog code for an unsigned 8-bit adder with carry in.

 module adder(a, b, ci, sum);
 input  [7:0] a;
 input  [7:0] b;
 input        ci;
 output [7:0] sum;
        
    assign sum = a + b + ci;

        endmodule 

Verilog code for an unsigned 8-bit adder with carry out.

 module adder(a, b, sum, co);
 input  [7:0] a;
 input  [7:0] b;
 output [7:0] sum;
 output       co;
 wire   [8:0] tmp;

    assign tmp = a + b;
    assign sum = tmp [7:0];
    assign co  = tmp [8];

        endmodule
        

Verilog code for an unsigned 8-bit adder with carry in and carry out.

        module adder(a, b, ci, sum, co);
        input        ci;
        input  [7:0] a;
        input  [7:0] b;
        output [7:0] sum;
        output       co;
        wire   [8:0] tmp;

           assign tmp = a + b + ci;
           assign sum = tmp [7:0];
           assign co  = tmp [8];

        endmodule
        

Verilog code for an unsigned 8-bit adder/subtractor.

 module addsub(a, b, oper, res);
 input        oper;
 input  [7:0] a;
 input  [7:0] b;
 output [7:0] res;
 reg    [7:0] res;
 always @(a or b or oper)
 begin
    if (oper == 1’b0)
       res = a + b;
    else
       res = a - b;
        end
        endmodule