Verilog Code for PRIORITY ENCODER using IF-ELSE

module pri_encoder_using_if (
  8 binary_out , //  4 bit binary output
  9 encoder_in , //  16-bit input 
 10 enable       //  Enable for the encoder
 11 );
 12 output [3:0] binary_out ;
 13 input  enable ; 
 14 input [15:0] encoder_in ; 
 15      
 16 reg [3:0] binary_out ;
 17       
 18 always @ (enable or encoder_in)
 19 begin
 20   binary_out = 0;
 21   if (enable) begin
 22    if (encoder_in[0] == 1) begin
 23     binary_out = 1; 
 24    end else if (encoder_in[1] == 1) begin
 25     binary_out = 2; 
 26    end else if (encoder_in[2] == 1) begin
 27     binary_out = 3; 
 28    end else if (encoder_in[3] == 1) begin
 29     binary_out = 4; 
 30    end else if (encoder_in[4] == 1) begin
 31     binary_out = 5; 
 32    end else if (encoder_in[5] == 1) begin
 33     binary_out = 6; 
 34    end else if (encoder_in[6] == 1) begin
 35     binary_out = 7; 
 36    end else if (encoder_in[7] == 1) begin
 37     binary_out = 8; 
 38    end else if (encoder_in[8] == 1) begin
 39     binary_out = 9; 
 40    end else if (encoder_in[9] == 1) begin
 41     binary_out = 10; 
 42    end else if (encoder_in[10] == 1) begin
 43     binary_out = 11; 
 44    end else if (encoder_in[11] == 1) begin
 45     binary_out = 12; 
 46    end else if (encoder_in[12] == 1) begin
 47     binary_out = 13; 
 48    end else if (encoder_in[13] == 1) begin
 49     binary_out = 14; 
 50    end else if (encoder_in[14] == 1) begin
 51     binary_out = 15; 
 52    end
 53   end
 54 end
 55 
 56 endmodule