vlsi world: verilog code for ACCUMULATOR

Saturday, 4 February 2012

verilog code for ACCUMULATOR

Verilog code for a 4-bit unsigned up accumulator with an asynchronous clear.

        module accum (clk, clr, d, q);
        input        clk, clr;
        input  [3:0] d;
        output [3:0] q;
        reg    [3:0] tmp;
        always @(posedge clk or posedge clr)
        begin
           if (clr)
              tmp <= 4’b0000;
           else
              tmp <= tmp + d;
        end
           assign q = tmp;
        endmodule

8 comments:

Ali2 January 2013 at 22:23
Showing an error..Syntax error !!!
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Electron4 March 2013 at 19:38
change ’ to '
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Anonymous20 April 2013 at 23:53
Wat is accumulator
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Unknown21 August 2013 at 22:08
can any one send verilog code for 3X3 matrix multiplication using memory
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yogananda12 May 2015 at 08:43
This comment has been removed by the author.
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yogananda12 May 2015 at 08:43
to get correct output use this:
if (clr)
tmp <= 0;
else
tmp <= d;
end
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pop4 May 2018 at 00:25
accumulator is a storing register memory for the logical and arithmetic data in cpu,
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Unknown23 September 2018 at 16:57
PLS SEND CODE FOR VEDIC MULTIPLIER USING YAVADANUM FORMULA
MAIL ID:dorathyabisha@gmail.com
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vlsi world

Saturday, 4 February 2012

verilog code for ACCUMULATOR

Verilog code for a 4-bit unsigned up accumulator with an asynchronous clear.
module accum (clk, clr, d, q); input clk, clr; input [3:0] d; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if (clr) tmp <= 4’b0000; else tmp <= tmp + d; end assign q = tmp; endmodule

8 comments:

blagorama

Saturday, 4 February 2012

verilog code for ACCUMULATOR

Verilog code for a 4-bit unsigned up accumulator with an asynchronous clear. module accum (clk, clr, d, q); input clk, clr; input [3:0] d; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if (clr) tmp <= 4’b0000; else tmp <= tmp + d; end assign q = tmp; endmodule

8 comments:

blagorama

Verilog code for a 4-bit unsigned up accumulator with an asynchronous clear.
module accum (clk, clr, d, q); input clk, clr; input [3:0] d; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if (clr) tmp <= 4’b0000; else tmp <= tmp + d; end assign q = tmp; endmodule