verilog code for ENCODER using CASE

module encoder_using_case(
  8 binary_out , //  4 bit binary Output
  9 encoder_in , //  16-bit Input
 10 enable       //  Enable for the encoder
 11 );
 12 output [3:0] binary_out  ;
 13 input  enable ; 
 14 input [15:0] encoder_in ; 
 15      
 16 reg [3:0] binary_out ;
 17       
 18 always @ (enable or encoder_in)
 19 begin
 20   binary_out = 0;
 21   if (enable) begin
 22     case (encoder_in) 
 23       16'h0002 : binary_out = 1; 
 24       16'h0004 : binary_out = 2; 
 25       16'h0008 : binary_out = 3; 
 26       16'h0010 : binary_out = 4;
 27       16'h0020 : binary_out = 5; 
 28       16'h0040 : binary_out = 6; 
 29       16'h0080 : binary_out = 7; 
 30       16'h0100 : binary_out = 8;
 31       16'h0200 : binary_out = 9;
 32       16'h0400 : binary_out = 10; 
 33       16'h0800 : binary_out = 11; 
 34       16'h1000 : binary_out = 12; 
 35       16'h2000 : binary_out = 13; 
 36       16'h4000 : binary_out = 14; 
 37       16'h8000 : binary_out = 15; 
 38    endcase
 39   end
 40 end
 41 
 42 endmodule